沙巴体育平台 www.yousuperb.com Micron this week hosted a grand opening ceremony of its Fab 10 Expansion in Singapore. The new cleanroom is not expected to increase the company’s production capacity in terms of wafer starts per month, but will enable Micron to continue adopting more advanced 3D NAND process technologies with a higher number of layers and bit density.

The new Fab 10 Expansion is an integral part of Micron’s Fab 10 complex that was previously comprised of Fab 10N and Fab 10X. Officially, it's known that the new 3D NAND production facility is built on a 165,000 m2 land plot, however Micron is not disclosing much else about the usable cleanroom space or other features of the expansion.

Micron is now installing equipment and expects to start production of 96-layer 3D NAND at the new Fab 10 Expansion sometime in the second half of this calendar year (i.e. in the next 4.5 months). Meanwhile, the company stresses that it will align its spending on production tools with 3D NAND demand and trends. Furthermore, even when fully equipped, the facility is not expected to add any new wafer capacity, but rather will be used to house more advanced process equipment necessary for greater numbers of 3D NAND layers.

As the number of 3D NAND layers increases, each wafer has to spend more time inside chemical vapor deposition (CVD) machines, meaning it takes longer to etch them. Adding more time still, various extravagant production techniques like string stacking lengthen manufacturing require even more steps. In order to keep the number of wafers processed consistent as the number of 3D NAND layers grows, flash memory producers have to add extra CVD and etching machines to cleanrooms, which requires extra space. As a result, while bigger fabs may not increase the number of wafer starts per month, they do enable growth in terms of produced NAND flash bits.

Along with the new manufacturing plant, Micron is also expanding its R&D operations in Singapore. Micron’s NAND Center of Excellence will among other things perform technology development and product engineering. Considering how close these functions will be to the actual production facility, the company certainly hopes to improve its yields and productivity at Fab 10.

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Sources: Micron, The Strait Times

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  • FreckledTrout - Friday, August 16, 2019 - link

    Thinking about 96-Layer 3D NAND just makes my head hurt. I can't believe the level of complexity we have arrived at to make NAND or for that matter the crazy things we have to do to use EUV to make the latest CPU's. The insane level of engineering going into computers today just blows my mind. Reply
  • quiksilvr - Friday, August 16, 2019 - link

    Wrap your brain around this: Samsung is already on 6th generation with 136-Layer 3D NAND.
    http://www.yousuperb.com/show/14721/samsung-unvei...
    Reply
  • nandnandnand - Saturday, August 17, 2019 - link

    What's important now is: where does it end? Are thousands or tens of thousands of layers doable without increasing die/package size too much?

    Hopefully, NAND will be replaced by a universal memory technology before we reach that point. Then all the space formerly used by DRAM and NAND can be occupied by universal memory. The universal memory could also be integrated into the CPU (3DSoC).
    Reply
  • ksec - Saturday, August 17, 2019 - link

    Forget about Universal Memory, that is a pipe dream, you will always have trade offs, From Bandwidth, Latency, Capacity, Power, and Cost.

    NAND could definitely see 512 / 1024 layers, so $50 / 1TB may only be a few years off.
    After that we don't know. Do we continue to optimise for Capacity ( which will drive down cost, something manufactures don't want ), or what?

    But that is at least 3 - 4 years off.
    Reply
  • 3DoubleD - Saturday, August 17, 2019 - link

    Hopefully where this is all going is price parity (or better) with mechanical hard drives, especially for WORM workloads. There seems to be a reasonable chance of this since $/GB has been pretty stagnant for many years in the mechanical hard drive market. Reply
  • ajp_anton - Saturday, August 17, 2019 - link

    Does the number of layers really lower the prices that much? Silicon area goes down, but costs per area goes up. Reply
  • 3DoubleD - Saturday, August 17, 2019 - link

    I can't presume to understand all of the factors, but based on what the industry has done it seems to be true that more layers leads to lower cost per bit. Early on we saw the transition between planar NAND, which scaled with traditional lithography nodes (smaller features leading to higher density NAND). The transition to 3D NAND accelerated the reduction trend of cost per bit and improved durability thanks to being able to fall back to larger feature sizes. Further increases in layers have led to further reductions of cost per bit. While adding more layers adds certain costs, like more CVD machines, they are fixed costs, which will be amortized over the life of the factory and over thousands of wafers. So while costs are higher, they are evidently less proportionately than the increase in bits per wafer. Reply
  • Billy Tallis - Sunday, August 18, 2019 - link

    The continued reductions in cost per bit are not being driven entirely or even predominantly by the increasing of layer count. That's already well beyond the point of diminishing returns, and increasing the layer count on its own really does increase costs by about the same amount that it increases density. The NAND manufacturers are working their way through a whole bag of other tricks to increase density and reduce cost, and in a lot of cases having a higher layer count means those other changes have a bigger impact. Reply
  • BurntMyBacon - Tuesday, August 20, 2019 - link

    @Billy Tallis: "The NAND manufacturers are working their way through a whole bag of other tricks to increase density and reduce cost"

    Certainly there are a number of fabrication optimizations that occur over the lifetime of any process node that can increase yields and reduce cost, but these cost reductions are realized as the process matures and cannot be associated with the initial cost reduction associated with moving to a new fabrication process (I.E. more layers). Given that the general architecture for NAND flash storage hasn't seen disruptive changes since charge traps, I'm drawing a blank as to what new "tricks" they may be using to increase bit density beyond the standard reduce area needed per bit (smaller feature sizes / process node) and increase usable area (larger chip, more layers, etc.). Please enlighten me to this bag of tricks that you state may be predominantly responsible for the cost reduction associated with new fabrication processes.
    Reply
  • nandnandnand - Saturday, August 17, 2019 - link

    Your idea of what is a pipe dream or 3-4 years off is hopelessly warped. We can already find 1 TB for about $85. Reply

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